PWM Modulator

The PWM modulator runs at the FPGA main clock. Therefore, the fundamental switching frequency is an integer division of the FPGA clock.

The modulation waveform is generated using a high-resolution lookup table (LUT) with linear interpolation to minimize ripple.

A classic sine waveform and a sine waveform with third-harmonic injection are available as default options.

Discontinuous modulation modes are also available to minimize switching transitions.

Assuming the sinusoidal modulator transfers 100% of the DC-link voltage to the motor, space-vector modulation can transfer more than 115%.

The DC-link voltage is evaluated at every PWM cycle.

A common-mode offset can optionally be added to eliminate narrow gate-drive pulses. The drawback is an increased switching activity.

PWM Modulator