Resolver
Sine–cosine to angle conversion
The Resolver IP consists of two separate modules.
In the Power Board FPGA IP, the resolver exciter must be implemented using the desired technology (FPGA-assisted, full-analog solution, or mixed-mode design).
In the Motor Control FPGA IP, the Resolver IP decodes the SINE/COSINE/EXCITER analog inputs to generate the motor electrical angle.
Two-channel SINE/COSINE-only sensors are also supported.
Linear interpolation is used to generate intermediate angles when the analog signal is not valid for direct evaluation.